1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor package having multilayer film carriers.
2. Description of the Related Art
As semiconductor chips have been developed in terms of operating speed, the number of pins and the performance, packages have been also developed for such semiconductor chips.
A semiconductor chip performance is affected by various parameters associated with its package. For example, a parasitic capacitance caused by a signal line serves as a capacitive load which affects the rising/falling speed and waveform of a signal on the signal line. Also, a parasitic inductance caused by a power supply line generates noise in response to a transient change of a power supply voltage due to a switching of a transistor. Further, a parasitic resistance caused by a power supply line or a signal line reduces the voltage thereof. Therefore, it is important to reduce the values of these parameters in the package.
Particularly, in a CMOS logic circuit, the reduction of the parasitic inductance is more important in order to reduce switching noise caused simultaneously by one of a PMOS transistor and an NMOS transistor being turned ON and by the other being turned OFF.
In a prior art ceramic type package, a multilayer substrate is adopted to reinforce power supply layers and ground layers, so that the parasitic inductances thereof are reduced. This will be explained later in detail.
Also, in a prior art lead frame type package which is typically called a quad flat package (QFP) (see JP-A-114461), a power supply layer and a ground layer are constructed by specified plane conductive layers, so that the parasitic inductances thereof can be reduced to about one third of a package where the power supply layer and the ground layer are constructed by a single layer. This will be also explained later in detail.
In the above-described prior art ceramic and lead frame type packages, however, bonding wiring systems are adopted. Therefore, as the number of pins is increased, the pitch of pads is made narrow, so that it is impossible to carry out a bonding operation between the pins and the pads. In addition, although the parasitic inductance caused by bonding wire is dependent upon the length and diameter thereof, this parasitic inductance cannot be ignored.
To avoid the drawbacks of the bonding wire systems, film carrier packages have been developed. For example, in a quad tape carrier package (Q-TCP) using a tape automated bonding (TAB) system, innerleads formed on an insulating film layer are bonded to bumps of a semiconductor chip, and outerleads are formed at the periphery of the package in the same way as in QFPs. Also, in a tape ball grid array (T-BGA), solder balls are arranged in a matrix.
In a first prior art film carrier type package, a double-layer structure is adopted. That is, an insulating film layer has a surface on which a lead frame is formed, and has another surface on which a ground layer is formed. The lead frame has innerleads and outerleads which are both connected via through holes. Thus, the self-inductance of the double-layer film carrier package is about 1/8 of that of the single-layer film carrier package. This will be also explained later in detail.
In the first prior art film carrier type package, however, the formation of small-diameter through holes increases the manufacturing cost; in other words, the manufacturing cost of the insulating film layer is increased. Also, when the number of pins is increased, the pins have to be more-fined, thus increasing the manufacturing cost. Further, it is difficult to adopt a multilayer structure such as triple-layer structure for the film carrier package, and therefore, a power supply layer cannot be provided.
In a second film carrier package (see JP-A-58-152375), a joining pad of a multilayer printed board including a power supply layer and a ground layer is adhered by a solder layer to an insulating film layer (suspender). Thus, the parasitic inductances of the power supply layer and the ground layer can be reduced. This will be also explained later in detail.
In the second prior art film carrier type package, however, a step for manufacturing the multilayer printed board and a step for adhering the multilayer printed board to the insulating film layer increase the manufacturing cost. In addition, in order to reduce the parasitic inductance, the joining pad is arranged in the proximity of a device hole so that the distance between the multilayer printed board and the semiconductor chip is reduced. In this case, a high grade fine pattern technology is required.
In a third prior art film carrier type package (see JP-A-5-218145), an insulating film layer having outerleads thereon is adhered to another insulating film layer having innerleads, so that the outerleads and the innerleads are staggeredly arranged. As a result, power supply pins and ground pins are dispersed, so that the widths of power supply layers and ground layers can be increased. Thus, the parasitic inductances of the power supply layers and the ground layers can be reduced. This will be also explained later in detail.
In the third prior art film carrier type package, however, since connections between the outerleads and the innerleads are realized via the through hole, a fine perforating process such as a punching process for the through hole is required. In this case, the distance between a semiconductor chip and a power supply layer (or a ground layer) is substantially increased. Therefore, when the number of pins is increased, a reduction of the parasitic inductance cannot be expected.
In a fourth prior art film carrier type package (see JP-A-5-226415), leads are alternately formed on both surfaces of an insulting film layer. Therefore, no through holes are required in the insulating film layer. This will be also explained later in detail.
In the fourth prior art film carrier type package, however, it is impossible to apply the leads alternately formed on the insulating film layer to a package where power supply layers, ground layers and signal line layers are dispersedly arranged. Also, since the package is limited to a double player structure, the improvement of electrical properties is insufficient. Further, since the leads are bent, short-circuits, displacement of the leads and deformation of the leads may be invited.